1. Field of the Invention
The present invention generally relates to a method of forming a semiconductor device. More specifically, the present invention relates to a method for manufacturing a semiconductor device that includes a step of forming a contact plug by chemical mechanical polishing (CMP).
Priority is claimed on Japanese Patent Application No. 2011-170208, filed Aug. 3, 2011, the content of which is incorporated herein by reference.
2. Description of the Related Art
A transistor is a typical semiconductor device, and planar structured transistors use the surface of a semiconductor substrate as a channel. In recent years, however, with the shrinking of semiconductor devices, it has become difficult to suppress the short channel effect in planar structured transistors, making it impossible to obtain the target transistor characteristics. Trench gate type transistors that use the surface of a trench formed within the semiconductor substrate have been widely used recently to solve the problem of the short channel effect.
Trench gate transistors are used also in DRAMs (dynamic random access memories). A trench gate transistor used in a DRAM (hereinafter DRAM transistor) is constituted by a memory cell region (hereinafter a cell region) and a peripheral circuit region. The cell region is partitioned into a plurality of cells by gate electrodes that function as word lines and bit lines formed in a direction that intersects the word lines. A contact plug that connects the semiconductor substrate with the upper interconnects is formed at each cell. Interconnects such as the word lines and bit lines and the contact plugs are formed, with respect to the minimum process dimension F of the semiconductor manufacturing equipment, with a size of approximately F, an integral multiple of F, or an integral fraction of F. A peripheral circuit region is provided in the area surrounding the cell region of a DRAM transistor. Circuitry to select a specific word line and bit line, and circuitry to control the voltages applied to the word lines and bit lines are built in the peripheral circuit region.
The minimum process dimension F of semiconductor manufacturing equipment is shrinking with the passage of time, and the density of the contact plugs in DRAM transistors is increasing. One method of forming densely spaced contact plugs is that of forming a hole-shaped aperture mask in the drain diffusion layer by a lithography process step, and forming an aperture part in an interlayer film over the drain diffusion layer by an etching step. Next, a conductive film of polysilicon or the like is filled into the aperture part, and CMP is used to polish the interlayer film and the conductive film.
Several proposals have already been made for such a semiconductor device surface polishing method that uses CMP.
Japanese Patent Application Publication No. JPA 2005-722238 discloses a polishing method whereby the polishing rates of an insulating film of the semiconductor device and polysilicon are controlled by fumed silica, ammonium hydroxide, and potassium hydroxide. According to this polishing method, even if damage occurs to the insulating film of the transistor during polishing, it is possible to suppress the occurrence of shorts and the like, and to form capacitor plugs that have uniform heights.
Japanese Patent Application Publication No. JPA 2002-305167 discloses a slurry and a polishing method wherein, the rate of removal of a silicon oxide film and a silicon nitride film is made smaller than with respect to the polysilicon of the semiconductor substrate, or the rate of removal of a silicon nitride film is made higher than that of the silicon oxide film. By using this polishing liquid, it is possible, while maintaining a high rate of removal of the polysilicon layer, to reduce the polishing rate of the silicon oxide film and silicon nitride film that are removed together with the polysilicon film.
U.S. Pat. No. 7,196,010 discloses a polishing method using a slurry that improves the selectivity ratio by making the silicon oxide film surface hydrophilic and making the polysilicon surface hydrophobic. According to the polishing method using this slurry, there is a great improvement in the selectivity ratio between the oxide film and the polysilicon film during polishing, and it is easy to achieve planarization within the cell.